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MC74LVX240DWR2

Descripción:
MC74LVX240DWR2 datasheet pdf and Logic - Buffers, Drivers, Receivers, Transceivers product details from Sanyo Semiconductor/ON Semiconductor stock available at Rozee
Categoría:
Circuitos integrados (CI)
Especificaciones
Part Number:
MC74LVX240DWR2
Manufacturer:
Sanyo Semiconductor/ON Semiconductor
Description:
In stock. Alternative models available.
Lifecycle:
New from this manufacturer
Delivery:
DHL、UPS、FedEx、Registered Mail
Payment:
T/T Paypal Visa MoneyGram Western Union
More Information:
MC74LVX240DWR2 More Information
ECAD:
Request Free CAD Models
Pricing(USD):
$0.00
Remark:
Manufacturer: Sanyo Semiconductor/ON Semiconductor. Rozee is one of the Distributors. Wide range of applications.
Mount:
Surface Mount
Packaging:
Tape and Reel
Logic Function:
Buffer, Inverter
Number of Pins:
20
Number of Outputs:
8
Quiescent Current:
4 µA
Min Supply Voltage:
2 V
Number of Circuits:
2
Turn-On Delay Time:
20 ns
Number of Input Lines:
8
Low Level Output Current:
4 mA
Max Operating Temperature:
85 °C
Products Category:
Integrated Circuits (ICs) - Logic - Buffers, Drivers, Receivers, Transceivers
Qty:
619 In Stock
Applications:
Building automation Electronic point of sale (EPOS) Enterprise machine
Polarity:
Inverting
Case/Package:
SOIC
Number of Bits:
8
Number of Inputs:
4
Propagation Delay:
9.7 ns
Max Supply Voltage:
3.6 V
Number of Channels:
8
Number of Elements:
2
Max Power Dissipation:
180 mW
Number of Output Lines:
3
High Level Output Current:
-4 mA
Min Operating Temperature:
-40 °C
Número de modelo:
MC74LVX240DWR2
Introducción
MC74LVX240DWR2 Overview\\nMC74LVX240DWR2 is a model belonging to the Logic - Buffers, Drivers, Receivers, Transceivers subcategory under Integrated Circuits (ICs). For specific product performance parameters, please refer to the data sheet, such as PDF files Docx documents, etc. We have MC74LVX240DWR2 high-definition pictures and data sheets for reference. We will continue to produce various video files and 3D models for users to understand our product more intuitively and
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